1. Field of the Invention
This invention relates to semiconductor fabrication, and more particularly to including a self-aligned silicide (Salicide) technology in fabrication of an embedded dynamic random access memory (DRAM).
2. Description of Related Art
Conventionally, an electronic device includes a logic circuit device and a memory device, which are separately fabricated in different individual semiconductor substrates. As the technologies of semiconductor fabrication are further developed, a new trend has developed in which the logic circuit device and the memory device are fabricated in a single substrate so as to enhance the operation speed. This kind of device layout is called an embedded DRAM, in which the DRAM is fabricated together with the logic circuit device in a substrate.
However, the fabrication processes for the logic device and the memory device are different. The logic device mainly used for a logic operation needs a fast data transmission speed, and therefore needs a self-aligned silicide (Salicide), such as titanium silicide, formed over the interchangeable source/drain regions to reduce sheet resistance. The memory device mainly used for storing information data needs to avoid leakage current, which leakage current may cause a change of data, and so the interchangeable source/drain regions must not have silicide.
FIGS. 1A-1E are perspective/cross-sectional views schematically illustrating a conventional fabrication process of an embedded DRAM. FIGS. 1F-1H are the cross-sectional views continuing from FIG. 1E. In FIG. 1A, a semiconductor substrate 100, such as a silicon substrate, is provided. The substrate 100 is divided into a logic device region 103 and a memory device region 105 by an isolating field oxide layer 101. An oxide layer 102 is formed over the substrate 100. An undoped polysilicon layer 104 is then formed over the substrate 100. A complementary metal-oxide semiconductor (CMOS) fabrication process is to be performed so as to form a P-type metal-oxide semi-conductor (MOS) transistor, that is, a PMOS transistor and an N-type MOS (NMOS) transistor. The fabrication process tarts from formation of a dual gate.
In FIG. 1B, a masking layer 108' is formed over the undoped polysilicon layer 104 so that a portion remains exposed. The exposed portion of the polysilicon layer 104 is doped by an N.sup.+ -type dopant 107' and results in a doped polysilicon layer 104'. The N.sup.+ -type polysilicon layer 104' is used for forming the NMOS transistor.
In FIG. 1C, after removing the masking layer 108', a masking layer 108" is formed to cover the N.sup.+ -type polysilicon layer 104'. A P.sup.+ -type dopant 107" is doped into the undoped polysilicon layer 104 of FIG. 1B so that a P.sup.+ -type polysilicon layer 104" is formed over the substrate 100. The P.sup.+ -type polysilicon layer 104" is used for forming the PMOS transistor. The N.sup.+ -type polysilicon layer 104' and the P.sup.+ -type polysilicon layer 104" abutting each other late form a dual gate structure.
In FIG. 1D, in order to increase the data transmission speed, a polycide layer 114 is formed over the substrate to cover the N.sup.+ -type polysilicon layer 104' and the P.sup.+ -type polysilicon layer 104".
In FIG. 1E, the polycide layer 114, the N.sup.+ -type polysilicon layer 104', the P.sup.+ -type polysilicon layer 104" and the pad oxide 102 are patterned to form two separate dual gate structures, one in the logic device region 103 and one in the memory device region 105. In the logic device region 103, the dual gate includes an oxide layer 102a, an N.sup.+ -type polysilicon layer 104a', a P.sup.+ -type polysilicon layer 104a", and a polycide layer 114a. Similarly, the dual gate structure in the memory device region 105 includes an oxide layer 102b, and N.sup.+ -type polysilicon layer 104b', a P.sup.+ -type polysilicon layer 104b", and a polycide layer 114b.
In this conventional process, the polycide layer 114 is not easily etched.
In FIG. 1F, using the dual gate structures and the isolation structure 101 as a mask, an ion implantation process is performed to lightly dope the silicon substrate 100 so as to form an interchangeable source/drain region with a lightly doped drain (LDD) structure. It is formed through following processes. A lightly doped region is formed on each side of the dual gate structures. A spacer 106 serving as a doping mask is formed on each sidewall of the dual gate structures. Then, a heavily doped region is formed by heavily doping the lightly doped region. After a rapid thermal process (RTP) to ensure a uniform distribution of the doped dopants, the interchangeable source/drain region with LDD structure is formed. The LDD structure includes a lightly doped region 109 under the spacer 106 with shallower doping depth and a heavily doped region 119 with greater doping depth.
In the above descriptions, rapid thermal process is used to form the interchangeable source/drain region of 109 and 119. This rapid thermal process causes an inter-layer diffusion at the interface between the N.sup.+ -type polysilicon layer 104a' and the P.sup.+ -type polysilicon layer 104a" through the polycide layer 114a. Similarly, an inter-layer diffusion also occurs at the interface between the P.sup.+ -type polysilicon layer 104b' and the P.sup.+ -type polysilicon layer 104b" through the polycide layer 114b. Moreover, the polycide layers 114a, 114b have poor thermal stability. For example, when RTP is performed, grains agglomerate in what is called a grain agglomerate phenomenon, which causes the polycide layer 114a, 114b, or any other kind of silicide layer, to easily crack. Such a crack deteriorates conductivity.
In FIG. 1G, an oxide layer 112b is formed only over the memory device region 105 to protect all metal-oxide semiconductor (MOS) transistors formed in the memory device region 105. In FIG. 1H, a self-aligned titanium silicide layer 124a is formed on the interchangeable source/drain region 119 in the logic device region 103.
The rest of the fabrication processes to form the embedded DRAM should be well known by one skilled in the art, and are not described here.
In summarization of the above descriptions, the conventional method for fabricating the embedded DRAM has some problems. Since the interchangeable source/drain region 119 in the memory device region 105 cannot have a silicide layer like the self-aligned silicide layer 124a in the logic device region 103, in order to reduce its resistance, the polysilicon layer is used for this purpose. On the contrary, it is desirable to form the self-aligned silicide layer 124a on the interchangeable source/drain region 119 in the logic device region 103. Thus, it is necessary to form the oxide layer 112b over the memory device region 105 before forming the self-aligned silicide layer 124a. This increases complexity of the fabrication process. Moreover, the polycide layer 114 is not easily etched. The polycide layer 114 also causes inter-layer diffusion at the interface between the N.sup.+ -type polysilicon layer 104a' and the P.sup.+ -type polysilicon layer 104a", and the interface between the N.sup.+ -type polysilicon layer 104b' and the P.sup.+ -type polysilicon layer 104b". Furthermore, the polycide layer 114 has poor thermal stability, which causes it to crack, and results in an increase of resistance.